Data integrity checking in flash memory operations has the goal of ensuring sure that the correct data is written to a flash memory device. For example, a controller typically performs a single integrity check on data to be written to a flash memory device prior to writing the data to the flash memory device. Such integrity checking is performed by computing and adding data parity bytes to data bytes to be written to the flash memory device and checking the parity before providing the data bytes to the flash memory device as part of a command sequence. If the data integrity checks passes, the command sequence is transmitted over a bus to the flash memory device. Depending on the nature of a data integrity failure, the command sequence may be re-created, and the data integrity check is re-attempted. Once the data integrity check is successful on the controller side, no further integrity checking is performed, and the data is transmitted over the bus and written to the flash memory array.
Transmission errors, i.e., errors that occur after the data parity check by the controller during transmission of data from the controller to the flash memory device, can cause errors in data written to flash memory. Such errors may be caused by board level disturbances or other disturbances that affect signal integrity. If the data becomes corrupted during transmission to the flash memory device, after the controller side data parity check, the incorrect data will be written to the flash memory array, and the error will not be discovered until the data is read back from the array. Writing incorrect data to the flash memory array not only wastes memory bandwidth and inefficiently uses storage resources, but may also reduce the correction capability of the error correction control (ECC) engine, which is the controller component that performs data parity checking, and increase power consumption.
The absence of error checking for address bytes can cause operations to be performed on incorrect address ranges. For NAND flash memory, the memory command and address cycles use conventional speed, for example, up to 50 MHz, which is much slower than the memory data transfer, for example, 200 MHz for Toggle Mode 400 and hence the likelihood of address integrity errors is low. However, as higher speed memories are used, higher speeds for command and address cycles may be used to further reduce latency. This may increase the susceptibility of address bytes to become corrupted due to transmission errors. If address bytes become corrupted, data can be written to the wrong address in program operations. In erase operations, if the address bytes are corrupted, the wrong block of memory will be erased. Data and address errors become even more likely in hierarchical memory systems where there are multiple controllers and bus interfaces between hosts and non-volatile memory cells.
Accordingly, there exists a need for methods, systems, and computer readable media for address and data integrity checking in flash memory operations.